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Assembly Source File  |  1994-02-14  |  7KB  |  140 lines
  1. *     TTL     FAST FLOATING POINT DUAL-BINARY FLOAT (FFPDBF)
  2. ************************************
  3. * (C) COPYRIGHT 1980 MOTOROLA INC. *
  4. ************************************
  5.  
  6. **********************************************************
  7. *                                                        *
  8. *          FAST FLOATING POINT DUAL-BINARY TO FLOAT      *
  9. *                                                        *
  10. *      INPUT:  D6 BIT #16 - REPRESENTS SIGN (0=POSITIVE) *
  11. *                                           (1=NEGATIVE) *
  12. *              D6.W - REPRESENTS BASE TEN EXPONENT       *
  13. *                     CONSIDERING D7 A BINARY INTEGER    *
  14. *              D7 -   BINARY INTEGER MANTISSA            *
  15. *                                                        *
  16. *      OUTPUT: D7 - FAST FLOATING POINT EQUIVALENT       *
  17. *                                                        *
  18. *      CONDITION CODES:                                  *
  19. *                N - SET IF RESULT IS NEGATIVE           *
  20. *                Z - SET IF RESULT IS ZERO               *
  21. *                V - SET IF RESULT OVERFLOWED            *
  22. *                C - CLEARED                             *
  23. *                X - UNDEFINED                           *
  24. *                                                        *
  25. *      REGISTERS D3 THRU D6 DESTROYED                    *
  26. *                                                        *
  27. *      CODE SIZE: 164 BYTES     STACK WORK AREA: 4 BYTES *
  28. *                                                        *
  29. *                                                        *
  30. *      PRECISION:                                        *
  31. *                                                        *
  32. *          THIS CONVERSION RESULTS IN A 24 BIT PRECISION *
  33. *          WITH GUARANTEED ERROR LESS THAN OR EQUAL TO   *
  34. *          ONE-HALF LEAST SIGNIFICANT BIT.               *
  35. *                                                        *
  36. *                                                        *
  37. *      NOTES:                                            *
  38. *          1) THE INPUT FORMATS HAVE BEEN DESIGNED FOR   *
  39. *             EASE OF PARSING TEXT FOR CONVERSION TO     *
  40. *             FLOATING POINT.  SEE FFPASF FOR COMMENTS   *
  41. *             DESCRIBING THE METHOD FOR SETUP TO THIS    *
  42. *             ROUTINE.                                   *
  43. *          2) UNDERFLOWS RETURN A ZERO WITHOUT ANY       *
  44. *             INDICATORS SET.                            *
  45. *          3) OVERFLOWS WILL RETURN THE MAXIMUM VALUE    *
  46. *             POSSIBLE WITH PROPER SIGN AND THE 'V' BIT  *
  47. *             SET IN THE CCR REGISTER.                   *
  48. *                                                        *
  49. **********************************************************
  50.          PAGE
  51. *FFPDBF   IDNT      1,1                 FFP DUAL-BINARY TO FLOAT
  52.  
  53. *         OPT       PCS
  54.  
  55.          XDEF      FFPDBF              ENTRY POINT
  56.          XREF      FFP10TBL            POWER OF TEN TABLE
  57.  
  58.  
  59. * NORMALIZE THE INPUT BINARY MANTISSA
  60. FFPDBF   MOVEQ     #32,D5    SETUP BASE 2 EXPONENT MAX
  61.          TST.L     D7        ? TEST FOR ZERO
  62.          BEQ       FPDRTN    RETURN, NO CONVERSION NEEDED
  63.          BMI.S     FPDINM    BRANCH INPUT ALREADY NORMALIZED
  64.          MOVEQ     #31,D5    PREPARE FOR NORMALIZE LOOP
  65. FPDNMI   ADD.L     D7,D7     SHIFT UP BY ONE
  66.          DBMI      D5,FPDNMI DECREMENT AND LOOP IF NOT YET
  67.  
  68. * INSURE INPUT 10 POWER INDEX NOT WAY OFF BASE
  69. FPDINM   CMP.W     #18,D6    ? WAY TOO LARGE
  70.          BGT.S     FPDOVF    BRANCH OVERFLOW
  71.          CMP.W     #-28,D6   ? WAY TOO SMALL
  72.          BLT.S     FPDRT0    RETURN ZERO IF UNDERFLOW
  73.          MOVE.W    D6,D4     COPY 10 POWER INDEX
  74.          NEG.W     D4        INVERT TO GO PROPER DIRECTION
  75.          MULS.W    #6,D4     TIMES FOUR FOR INDEX
  76.          MOVE.L    A0,-(SP)  SAVE WORK ADDRESS REGISTER
  77.          LEA       FFP10TBL,A0 LOAD TABLE ADDRESS
  78.          ADD.W     0(A0,D4.W),D5 ADD EXPONENTS FOR MULTIPLY
  79.          MOVE.W    D5,D6     SAVE RESULT EXPONENT IN D6.W
  80.  
  81. * NOW PERFORM 32 BIT MULTIPLY OF INPUT WITH POWER OF TEN TABLE
  82.          MOVE.L    2(A0,D4.W),D3 LOAD TABLE MANTISSA VALUE
  83.          MOVE.L    (SP),A0   RESTORE WORK REGISTER
  84.          MOVE.L    D3,(SP)   NOW SAVE TABLE MANTISSA ON STACK
  85.          MOVE.W    D7,D5     COPY INPUT VALUE
  86.          MULU.W    D3,D5     TABLELOW X INPUTLOW
  87.          CLR.W     D5        LOW END NO LONGER TAKES AFFECT
  88.          SWAP.W    D5        SAVE INTERMEDIATE SUM
  89.          MOVEQ     #0,D4     CREATE A ZERO FOR DOUBLE PRECISION
  90.          SWAP.W    D3        TO HIGH TABLE WORD
  91.          MULU.W    D7,D3     INPUTLOW X TABLEHIGH
  92.          ADD.L     D3,D5     ADD ANOTHER PARTIAL SUM
  93.          ADDX.B    D4,D4     CREATE CARRY IF ANY
  94.          SWAP.W    D7        NOW TO INPUT HIGH
  95.          MOVE.W    D7,D3     COPY TO WORK REGISTER
  96.          MULU.W    2(SP),D3  TABLELOW X INPUTHIGH
  97.          ADD.L     D3,D5     ADD ANOTHER PARTIAL
  98.          BCC.S     FPDNOC    BRANCH NO CARRY
  99.          ADDQ.B    #1,D4     ADD ANOTHER CARRY
  100. FPDNOC   MOVE.W    D4,D5     CONCAT HIGH WORK WITH LOW
  101.          SWAP.W    D5        AND CORRECT POSITIONS
  102.          MULU.W    (SP),D7   TABLEHIGH X INPUTHIGH
  103.          LEA       4(SP),SP  CLEAN UP STACK
  104.          ADD.L     D5,D7     FINAL PARTIAL PRODUCT
  105.          BMI.S     FPDNON    BRANCH IF NO NEED TO NORMALIZE
  106.          ADD.L     D7,D7     NORMALIZE
  107.          SUBQ.W    #1,D6     ADJUST EXPONENT
  108. FPDNON   ADD.L     #$80,D7   ROUND RESULT TO 24 BITS
  109.          BCC.S     FPDROK    BRANCH ROUND DID NOT OVERFLOW
  110.          ROXR.L    #1,D7     ADJUST BACK
  111.          ADDQ.W    #1,D6     AND INCREMENT EXPONENT
  112. FPDROK   MOVEQ     #9,D3     PREPARE TO FINALIZE EXPONENT TO 7 BITS
  113.          MOVE.W    D6,D4     SAVE SIGN OF EXPONENT
  114.          ASL.W     D3,D6     FORCE 7 BIT PRECISION
  115.          BVS.S     FPDXOV    BRANCH EXPONENT OVERFLOW
  116.          EORI.W    #$8000,D6 EXPONENT BACK FROM 2'S-COMPLEMENT
  117.          LSR.L     D3,D6     PLACE INTO LOW BYTE WITH SIGN
  118.          MOVE.B    D6,D7     INSERT INTO RESULT
  119.          BEQ.S     FPDRT0    RETURN ZERO IF EXPONENT ZERO
  120. FPDRTN   RTS                 RETURN
  121.  
  122. * RETURN ZERO FOR UNDERFLOW
  123. FPDRT0   MOVEQ     #0,D7     LOAD ZERO
  124.          RTS                 RETURN
  125.  
  126. * EXPONENT OVERFLOW/UNDERFLOW
  127. FPDXOV   TST.W     D4        TEST ORIGINAL SIGN
  128.          BMI.S     FPDRT0    BRANCH UNDERFLOW TO RETURN ZERO
  129. FPDOVF   MOVEQ     #-1,D7    CREATE ALL ONES
  130.          SWAP.W    D6        SIGN TO LOW BIT
  131.          ROXR.B    #1,D6     SIGN TO X BIT
  132.          ROXR.B    #1,D7     SIGN INTO HIGHEST POSSIBLE RESULT
  133.          TST.B     D7        CLEAR CARRY BIT
  134. *        ORI       #$02,CCR  SET OVERFLOW ON
  135.          DC.L      $003C0002 ****ASSEMBLER ERROR****
  136.          RTS                 RETURN TO CALLER WITH OVERFLOW
  137.  
  138.  
  139.          END
  140.